The present invention relates to a semiconductor design technology, and more particularly, to a reference memory cell for providing a reference current in a semiconductor memory device employing a Magnetic Tunnel Junction (MTJ) device.
Generally, it is known that Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM) devices that are volatile memory devices have a disadvantage where data stored in their memory cells can be lost when power is not supplied thereto. Thus, studies have been carried out to develop nonvolatile memory devices in recent years. One example of nonvolatile memory devices is a Magnetic Random Access Memory (MRAM) device that is a type of magnetic memory device. In particular, since the MRAM device has nonvolatile characteristics, achieves high integration and has high-speed operation and low power consumption characteristics, it has drawn a lot of attention as a next generation semiconductor memory device.
Each memory cell of the MRAM device may be composed of one transistor for performing a switching operation in response to an address provided from outside, and an MTJ device for storing data or information. The MTJ device, which is a type of magnetic memory device and has characteristics where MagnetoResistance (MR) varies depending on a magnetization direction of ferromagnetic, detects current by variations of MR to determine whether data stored in the MTJ device is ‘1’ or ‘0’.
FIG. 1 is a circuit diagram illustrating the structure of a memory cell in a conventional semiconductor memory device.
Referring to FIG. 1, the memory cell includes one NMOS transistor 110 and one MTJ device 130.
The NMOS transistor 110 has a source-drain path formed between a source line SL and the MTJ device 130 and a gate connected to a word line WL, and is turned on or off depending on whether the word line WL is activated or deactivated. Here, the word line WL is selected by a row address.
The MTJ device 130 is composed of a free layer 132, a tunnel isolation layer 134, and a pinned layer 136. Here, the free layer 132 is made of ferromagnetic, in which its magnetization direction varies with an external stimulation (e.g., current transmitted to the MTJ device 130). But, the pinned layer 136 has a magnetization direction that does not vary although an external stimulation is applied. For reference, the pinned layer 136 has a fixed magnetization direction by a pinning layer (not shown) made of antiferromagnetic, and the tunnel isolation layer 134 may be formed of, for example, Magnesium Oxide (MgO) layer.
Such an MTJ device 130 has a tunneling current flowing depending on a certain voltage applied to its ends, in which the magnetization direction of the free layer 132 is determined depending on a direction of the tunneling current. If the magnetization direction of the free layer 132 is consistent with that of the pinned layer 136, the MTJ device 130 has a smaller resistance value, and if the magnetization direction of the free layer 132 is not consistent with that of the pinned layer 136, the MTJ device 130 has a greater resistance value (for example, a resistance value greater than the smaller resistance value). In general, if the magnetization direction of the free layer 132 is consistent with that of the pinned layer 136, data has ‘0’, and if not, it has ‘1’.
In other words, in case where a positive voltage is applied to the free layer 132 to cause a positive current larger than a threshold current to flow therein, the magnetization direction of the free layer 132 becomes consistent with that of the pinned layer 136. Here, the positive voltage to the free layer 132 is greater than that to the pinned layer 136 by a certain amount. That is, a write operation of ‘0’ data is performed and a resistance value of the MTJ device 130 becomes smaller. In contrast, in case where a negative voltage is applied to the free layer 132 to cause the negative current larger than a threshold current to flow therein, the magnetization direction of the free layer 132 becomes opposite to that of the pinned layer 136. Here, the positive voltage to the free layer 132 is greater than that to the pinned layer 136 by a certain amount. That is, a write operation of ‘1’ data is performed and a resistance value of the MTJ device 130 becomes greater.
FIG. 2 shows characteristics of current and resistance that depend on temperature and voltage of the MTJ device 130 in FIG. 1.
As can be seen from FIG. 2, the MTJ device 130 has hysteresis, and also has two stable states depending on positive/negative currents above a threshold voltage, that is, a state with a smaller resistance value and a state with a larger resistance value. Such stable states continue to be maintained even with no power being applied.
FIG. 3 is a circuitry diagram illustrating the configuration of a conventional semiconductor memory device.
Referring to FIG. 3, the conventional semiconductor memory device includes a plurality of memory cells 310, a plurality of reference memory cells 320, a data current generation unit 330, a reference current generation unit 340, a sense amplification unit 350, a source line drive unit 360, a bit line drive unit 370, and first and second line drive units 380 and 390.
Each of the memory cells 310 serves to store data, and is provided with an NMOS transistor NM for performing a switching operation in response to an address, and an MTJ device for storing data, as described in FIG. 1. The memory cells 310 are configured to correspond to a plurality word lines WL0, WL1, . . . , WLn, respectively, and are connected between a source line SL and a bit line BL. A data write operation of the memory cells 310 will be described later.
Each of the reference memory cells 320 generates a reference current I_REF and has the similar configuration to that of the memory cells 310, in which two reference memory cells is arranged in group to correspond to one word line. For illustration purposes, two reference memory cells corresponding to one word line will be referred to as a ‘reference memory cell group’ below. In general, two reference memory cells included in every reference memory cell group should have ‘1’ data and ‘0’ data stored therein, prior to producing semiconductor memory devices. That is, one reference memory cell should be an MTJ device RH having a larger resistance value, while the other reference memory cell should be an MTJ device having a smaller resistance value (e.g., a resistance smaller than the larger resistance value). The reason for storing ‘0’ and ‘1’ data with different polarities in every reference memory cell group is because the MTJ device has the characteristic shown in FIG. 2. Each of the reference memory cells 320 performs the operation of providing a reference current I_REF depending on the state of selected memory cell. A data write operation of the reference memory cells 320 will be described later.
The data current generation unit 330 generates a data current I_DAT corresponding to a memory cell selected by the word lines WL0, WL1, . . . , WLn, among the memory cells 310, and is composed of a current mirror. During a read operation, current corresponding to data stored in the selected memory cell flows in the bit line BL, in which an amount of the data current I_DAT is the same as that flowing in the bit line BL.
The reference current generation unit 340 generates a reference current I_REF corresponding to a reference memory cell group selected by the word lines WL0, WL1, . . . , WLn. Here, an amount of the reference current I_REF has half of an amount of current flowing in the selected reference memory cell group. That is, the reference current I_REF has half of a summed value of an amount of current flowing in the MTJ device RH with a larger resistance value and an amount of current flowing in the MTJ device RL with a smaller resistance value.
The sense amplification unit 350 senses and amplifies the data current I_DAT and the referent current I_REF. That is, the sense amplification unit 350 receives the fixed reference current I_REF of the reference memory cell group corresponding to the selected word line and the data current I_DAT varying depending on data in a memory cell corresponding to the selected word line, and compares them to output a comparison result. Then, based on the comparison result, the data stored in the memory cell can be determined from the outside.
The source line drive unit 360 and the bit line drive unit 370 drive the source line SL and the bit line BL depending on data to store desired data in corresponding memory cells, respectively. That is, the source line drive 360 drives the source line SL by a core voltage VCORE or ground voltage VSS depending on data, and the bit line drive 370 drives the bit line BL by the core voltage VCORE or ground voltage VSS depending on data.
Hereinafter, a data write operation of a memory cell will be briefly described. For illustration purposes, it is assumed that any one word line that corresponds to a memory cell where a write operation is performed, among the word lines WL0, WL1, . . . , WLn, is activated. During the write operation, a bit line selection signal BS is activated and the bit line BL is driven by the bit line drive unit 370.
First, during the write operation of ‘1’ data, the source line drive unit 360 drives the source line SL by the core voltage VCORE, and the bit line drive unit 370 drives the bit line BL by the ground voltage VSS. Therefore, current flows from the source line SL to the bit line BL via the MTJ, so that the ‘1’ data is stored in the memory cell, as described in FIG. 1.
Next, during the write operation of ‘0’ data, the source line drive unit 360 drives the source line SL by the ground voltage VSS, and the bit line drive unit 370 drives the bit line BL by the core voltage VCORE. Therefore, current flows from the bit line BL to the source line SL via the MTJ, so that the ‘0’ data is stored in the memory cell, as described in FIG. 1.
Meanwhile, the first and second line drive units 380 and 390 drive reference source and bit lines to store corresponding data in the reference memory cells 320. Specifically, the first line drive unit 380 drives a reference source line REF_SL by the core voltage VCORE or ground voltage VSS depending on data to be stored, and the second line drive unit 390 drives first and second reference bit lines REF_BL1 and REF_BL2 by the core voltage VCORE or ground voltage VSS depending on data to be stored.
Hereinafter, a data write operation of reference memory cells will be briefly described. For illustration purposes, it is assumed that any one of the word lines WL0, WL1, . . . , WLn is activated.
First, during the write operation of ‘1’ data, a first drive control signal REF_H becomes logic ‘high’, and thus a first NMOS transistor NM1 is turned on. Meanwhile, the first line drive unit 380 drives the reference source line REF_SL by the core voltage VCORE, and the second line drive unit 390 drives the first reference bit line REF_BL1 by the ground voltage VSS. Therefore, current flows from the reference source line REF_SL to the first reference bit line REF_BL1 via the MTJ device RH, so that ‘1’ data is stored in the MTJ device RH. That is, the MTJ device RH has a larger resistance value.
Next, during the write operation of ‘0’ data, a second drive control signal REF_L becomes logic ‘high’, and thus a second NMOS transistor NM2 is turned on. Meanwhile, the first line drive unit 380 drives the reference source line REF_SL by the ground voltage VSS, and the second line drive unit 390 drives the second reference bit line REF_BL2 by the core voltage VCORE. Therefore, current flows from the second reference bit line REF_BL2 to the reference source line REF_SL via the MTJ device RL, so that ‘0’ data is stored in the MTJ device RL. That is, the MTJ device RL has a smaller resistance value. 0028 The reference memory cells 320 have the MTJ device RH with a larger resistance value and the MTJ device RL with a smaller resistance value through the foregoing operation. In other words, in order to make the ‘1’ data and ‘0’ data stored in a reference memory cell group corresponding to one word line, the word line should be activated and the corresponding reference memory cell is selected by the first and second drive control signals REF_H and REF_L, and then the first and second line drive units 380 and 390 should be operated. For the following operation for storing ‘1’ data and ‘0’ data in another reference memory cell group, the foregoing operation should be repeated for the corresponding word line.
Meanwhile, as mentioned above, the reference memory cells 320 should have ‘1’ data and ‘0’ data written therein prior to producing the semiconductor memory device. The write operation of the reference memory cells 320 inevitably requires certain time and power consumption. If considerable time and power are required for storage of data in the memory cells 320, the semiconductor memory device incorporating them has competitive disadvantages.